1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit capable of executing any one of five existing integrated circuit test modes, a PS (Positive to VSS) test mode, an NS (Negative to VSS) test mode, a PD (Positive to VDD) test mode, an ND (Negative to VDD) test mode, and a DS (VDD to VSS) test mode.
2. Description of the Prior Art
In recent years, owing to a dramatic progress in integrated circuit (IC) technologies an IC, which is composed of a plurality of complementary metal oxide semiconductors (CMOSs), can have a size reduced from some microns to hundreds or even tens of deep-submicrons, to pursue goals of lower cost and better operation efficiency. However, a smaller IC has weaker ESD protection capability accordingly. For example, if an output buffer component is assumed to have a 300 micrometer channel width, an NMOS manufactured according to a two-micrometer conventional IC manufacturing process can have an ESD protection capability to endure an ESD voltage having a voltage level as high as three thousand volts, but another IC manufactured according to a one-micrometer lightly-doped drain process is capable of enduring an ESD voltage having a voltage level of only two thousand volts. Moreover, since electrostatic charges in an environment where an IC is located are constant and irrelevant with the size of the IC, an IC of a smaller size is easier to be damaged by ESD charges than a larger-sized IC. Therefore, as ICs become smaller, ESD protection circuits used to protect ICs from damage induced by ESD charges are becoming one of the most important types of electronic circuits.
In general, an ESD can be defined according to four models: a human-body model (HBM), a charged-device model (CDM), a machine model (MM), and a field-induced model (FIM). The HBM is described briefly as an example. A human's movement induces electrostatic charges. When the induced electrostatic charges exceed a threshold value and the human, on whom the electrostatic charges are accumulated, contacts an IC chip, the electrostatic charges will flow to ground through a pin and an inner circuit of the IC chip. Such an electrostatic discharging process induces a transient discharging current having a few amps, which is large enough to burn out the IC chip in a short period (hundreds of nanoseconds).
Please refer to FIG. 1, which is an equivalent circuit diagram illustrating an HBM model 10 and an ESD protection circuit 15 for preventing an IC chip 16 from damage induced by ESD charges generated by a human being according to the prior art. The ESD protection circuit 15 comprises an equivalent resistor 17 and an equivalent capacitor 19. The equivalent capacitor 19 is assumed to be one CESD in capacitance. Initially, the ESD charges induced from the movement of the human will accumulate on an equivalent capacitor (100 pF) 12. When the human contacts the IC chip 16 (in equivalent, a switch 18 connects to point B.), the ESD charges accumulated on the equivalent capacitor 12 will travel to ground through an equivalent resistor 14 (1.5K Ω), the equivalent resistor 17, and the equivalent capacitor 19 sequentially, without entering the IC chip 16. Thus, the IC chip 16 is free from damage induced by the ESD charges.
In general, five ESD test modes, a PS, an NS, a PD, an ND and a DS ESD test mode, are applied to evaluate an ESD protection capability of an IC chip. Please refer to FIG. 2, which is a schematic diagram illustrating how the PS ESD test mode evaluates the ESD protection capability of the IC chip 16 according to the prior art. The IC chip 16 comprises a VSS pin 24 electrically connected to ground, a pin 22, ready to be test, electrically connected to a positive test voltage 20, and a plurality of floated pins including a VDD pin 26.
According to the PS ESD test mode, the positive test voltage 20 is applied to the pin 22 with a first predetermined positive voltage a couple of times, usually three times, to test if the pin 22 is still robust despite the shock of the positive test voltage 20. The positive test voltage 20 is equivalent to ESD charges. If the pin 22 is still functioning normally, the positive test voltage 20 is raised to a second predetermined positive voltage and again applied to the pin 22 three times. The positive test voltage 20 is raised again and applied to the pin 22 until the pin 22 is damaged by the positive test voltage 20 of a predetermined positive voltage, which is called an ESD failure threshold. A plurality of methods, such as an absolute leakage current method, relative I-V drift method, and a function detection method, are used to determine if the pin 22 of the IC chip 16 is damaged due to ESD charges.
As mentioned earlier, there are five ESD test modes used to evaluate the ESD protection capability of the IC chip 16. The five test modes have five corresponding ESD failure thresholds different from each other. The ESD failure threshold of the pin 22 of the IC chip 16 calculated above corresponds only to the PS ESD test mode, one of the five ESD test modes. Moreover, in the IC chip 16 the ESD failure threshold of the pin 22 is usually different from that of any other pins even if they are evaluated according to an identical ESD test mode. The IC chip 16 cannot function normally unless all the pins can survive ESD charges. Therefore, a smallest ESD failure threshold in an ESD failure threshold group consisting of a plurality of ESD failure thresholds calculated according to the five ESD test modes governs, and is a genuine ESD failure threshold of the IC chip 16.
Because which of the ESD failure thresholds in the ESD failure threshold group is to be the genuine ESD failure threshold of the IC chip 16 is uncertain, the ESD protection circuit 15 that protects the IC chip 16 from damage induced by ESD charges having levels higher than the genuine ESD failure threshold has to have the capability to survive ESD charges provided by the five above-mentioned ESD test modes. Please refer to FIG. 3, which is a schematic diagram of the IC chip 16 according to the prior art. Each pin of the IC chip 16 has to be evaluated according to the five ESD test modes, as described previously, and the pin 22 acting as an input pad as well as an output pad is described here as an example. The IC chip 16 comprises an inner circuit 30 and five ESD protection circuits 32, 34, 36, 38 and 40 for protecting the inner circuit 30 from ESD charges provided by the five ESD test modes respectively. The ESD protection circuits 32 to 40 are dedicated to protect the inner circuit 30 from ESD charges, and therefore do nothing if the IC chip does not suffer any ESD charges.
The operation of the IC chip 16 under ESD charges in accordance with the ND ESD test mode is described briefly as follows: Current induced by the ESD charges flows from the VDD pin 26, through the ESD protection circuits 36 and 32, along the VSS pin 24, through the ESD protection circuit 34 and the input pad 22, and eventually to a negative test voltage 42. According to such a scenario, the IC chip 16 is free from the impact induced by the negative test voltage 42, the ESD charges in equivalence.
A variety of CMOS ICs, such as diffusion or poly resistors, p-n junction diodes, MOS components, bipolar junction transistors, and silicon-controlled rectifier (SCR) components, are implemented to form ESD protection circuits. These components have distinct characteristics and ESD protection capability.
For example, since a forward-biased diode has a working voltage (about 0.8 to 1.2 volts) far smaller than that (about −13 to −15 volts) of a reverse-biased diode, and heat generated by the forward-biased diode is accordingly far smaller than that of the reverse-biased diode if ESD currents flowing through these two diodes are equal. The forward-biased diode has an ESD protection capability far superior to that of the reverse-biased diode if their sizes are equal. A diode that an ESD protection circuit comprises is usually forward-biased. However, an ESD protection circuit having a diode installed has to comprise an additional component such as a resistor. On the other hand, since both a reverse-biased and a forward-biased SCR component have a constant working voltage equal to one volt, an SCR component of small size still has satisfactory ESD protection capability. Manufactured according to an identical process, an SCR component has an ESD protection capability per unit area is superior to that of any of the diffusion or poly resistors, the p-n junction diodes, the MOS components, and the bipolar junction transistors.
The above-mentioned MOS ICs can be composed to form a variety of ESD protection circuits. Please refer to FIG. 4 and FIG. 5, which are two circuit diagrams of two ESD protection circuits 50 and 60 electrically connected between the pin 22 and the inner circuit 30 for protecting the inner circuit 30 from damage induced by ESD charges. Both of the ESD protection circuits 50 and 60 are composed of at least two of the above-mentioned MOS ICs. The ESD protection circuit 50 comprises a resistor 52 and two cascaded diodes 54 and 56. The ESD protection circuit 60 comprises two cascaded resistors 62 and 64, an SCR component 66, and a field-oxide device 68. The ESD protection circuit 50 has an ESD capability superior to that of the ESD protection circuit 40.
As mentioned previously, an ESD capability of an ESD protection circuit relates to the MOS ICs that the ESD protection circuit comprises. However, any improvement of these MOS ICs also has the benefit of promoting the ESD protection capability of the ESD protection circuit. In general, the ESD protection capability of a CMOS component can be improved in three aspects including manufacturing process, the component itself and circuit design.
As far as the first aspect of the manufacturing process is concerned, although a variety of techniques such as implanting an LDD structure into a CMOS, applying Silicided diffusion to a diffusion layer of a MOS component, reducing stray serial resistance on the gate of a MOS component with Polycide, and adopting a process consisting of Silicided diffusion and Polycide, can be used to increase the density and operation speed of an inner circuit of a MOS, the MOS has a poor ESD protection capability and is susceptible to ESD charges. Two manufacturing processes, an ESD-implant process and a silicided-diffusion blocking process, are used to solve the above problem. The ESD-implant process executes an ion implanting process one more time on a drain of a CMOS, so that currents flowing through the drain are evenly distributed and the CMOS has a better ESD protection capability. The silicided-diffusion blocking process has a capability to control a ballasting resistor between the drain and gate of the MOS component, so as to increase the operation speed of the CMOS component.
As far as the second aspect of the component itself is concerned, a well-known low-voltage triggering SCR (LVTSCR) is described briefly as an example. The LVTSCR comprises a P+ diffusion layer, an N-well layer, a P-substrate layer, and an N+ diffusion layer. Having a high junction breakdown threshold, about 30 to 50 volts, the LVTSCR has to have an additional clamp circuit installed. When turned on due to an ESD voltage induced by ESD charges, the LVTSCR generates a clamping voltage, which has a capability to protect an inner circuit protected by the LVTSCR by clamping the ESD voltage down to a low voltage level.
As far as the third aspect of the circuit design is concerned, a gate-coupled technique applied to NMOS components, a gate-grounded technique, and a substrate-triggered technique are three popular techniques. A large-sized component usually has a finger-typed layout. However, these fingers connected in parallel are usually not conducted to release an ESD current simultaneously. This is the reason why an ESD protection capability of a component is not proportional to a size of the component. The substrate-triggered technique is capable of improving the ESD protection capability of a component by uniformly conducting all of the fingers according to a capacitance effect. The gate-grounded technique is capable of releasing ESD current effectively by electrically connecting a drain and a gate of a MOS component to a pin and to ground respectively and conducting a parasitic bipolarjunction diode (BJT) of the MOS component. The gate-coupled technique offers a great contribution to conduct the parasitic BJT by controlling a voltage level of the gate with a capacitance coupling method. As described previously, five ESD test modes have to be used to evaluate an ESD protection capability, and a single MOS is capable of achieving at least two ESD test modes, so an ESD protection circuit has to comprise at least three MOS components.
In general, an ESD protection circuit of the prior art has at least the following disadvantages:
1. The ESD protection circuit will impose a load effect on an inner circuit and reduces the efficiency as a whole;
2. The ESD protection circuit generates a large leakage current and has a great power consumption;
3. The ESD protection circuit needs a driving voltage having a high voltage level and releases ESD currents inefficiently;
4. The ESD protection circuit cannot protect itself from damage induced by ESD charges, and has a poor ESD protection capability to protect an inner circuit protected by the ESD protection circuit;
5. The ESD protection circuit does not have uniformly distributed currents, so that even if the ESD protection circuit has an area dramatically increased, an ESD protection capability of the ESD protection circuit still only increases slightly;
6. The ESD protection circuit has to comprise at least to three ESD components to achieve all of the five ESD test modes;
7. An additional process such as an ESD implant process is used to fabricate the ESD protection circuit, making the ESD protection circuit have a higher cost; and
8. The ESD protection circuit cannot be applied to a broadband radio circuit.